Bits + chips
Mentor Graphics Veloce VirtuaLAB adds protocols for networking designs
Michael McManus, DIGITIMES, Taipei

Mentor Graphics has announced its Veloce VirtuaLAB Ethernet environment with support for 25Gb, 50Gb and 100Gb Ethernet designs. VirtuaLAB is Mentor Graphics' platform for delivering what it calls a fully virtual, block to system level accelerated verification flow for emulation users, by replacing the traditional physical devices used in In-circuit Emulation (ICE) with virtual devices.

While previously supporting Ethernet SoC design development with VirtuaLAB, the company has now extended support to the higher-speed Ethernet environment due to the sheer complexity of networking designs. With the large number of ports, expanding throughput, decreasing latency, and improvements in security and ease-of-use, current designs are reaching a half billion gates, the company indicated. Only the largest processor and graphics chips are bigger than current network switch and router designs.

For these complex designs (say for a 128-port Ethernet interface with a variable bandwidth of 1/10/40/100/120Gbps), hardware description language (HDL) simulation can be used at the block level, but verification of an entire design of several hundred million gates with simulated traffic is unrealistic. So up to this point hardware emulation has been used for in-circuit-emulation (ICE) mode.

However, an ICE configuration requires one Ethernet tester per port. And since a direct connection is not possible due to the different speed domains between the tester and the emulated design under test (DUT), a speed rate adapter is inserted between the two, making the overall setup complex and problematic. Moreover, the entire setup supports only a single user located in the proximity of the emulation lab, Mentor Graphics noted.

An equivalent solution using a virtual approach is provided by Mentor Graphics' Ethernet VirtuaLAB. Under this scenario, the Ethernet testers are modeled in software running under Linux on a workstation connected to the emulator, the company explained. This virtual tester includes an Ethernet packet generator and monitor (EPGM) that generates, transmits and monitors Ethernet packets with the DUT. It also has the ability to configure GMII, XGMII, XLGMII/CGMII and CXGMII interfaces for 1Gb, 10Gb, 40Gb/100Gb and 120Gb, respectively.

VirtuaLAB components provide a complete software-driven Ethernet stack that runs at up to 15,000 times the speed of traditional simulation, Mentor Graphics claims. If that is the case, it would let VirtuaLab Ethernet users tackle the complex challenges of Ethernet-based designs with improved throughput, advanced debug, power analysis and performance analysis.

In addition, the virtualization moves emulation from the engineering lab to the computing datacenter.

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