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News tagged wafer-level packaging
  • Last update: Thursday 20 July 2017 [40 news items]

TSMC InFO packaging brings more competitiveness to its 7nm process technology

Jul 20, 11:45

Taiwan Semiconductor Manufacturing Company's (TSMC) integrated fan-out (InFO) wafer-level packaging technology is about to enter its second generation, which will bring more competitiveness...

Packaging can extend physical limits of semiconductors, says TSMC chair

Jun 12, 15:41

Moore's Law will reach its physical limits in 8-10 years, but the development of advanced packaging technology will help extend innovations, according to Morris Chang, chairman of...

TSMC chairman Morris Chang

Micron talks about its integrated global operations

Apr 26, 15:37

Micron Technology has been actively allocating its global resources to enhance its DRAM and NAND flash product lines, according to Wayne Allan, VP of global manufacturing at the US-based...

Wayne Allan, VP of global manufacturing at Micron

Amkor to buy fellow packaging company Nanium

Feb 8, 10:39

Amkor Technology and Nanium, a Portugal-based IC backend house specializing in wafer-level fan-out (WLFO) packaging solutions, have entered into a definitive agreement for Amkor to...

Fujifilm to open new plant for advanced IC materials in Taiwan

Nov 14, 23:05

Fujifilm has announced that its semiconductor business subsidiary, Fujifilm Electronic Materials, will launch the operation of its third plant in Taiwan in late November. The new...

ASE ready to enter volume production of fan-out wafer-level packaging

Oct 26, 11:54

Advanced Semiconductor Engineering (ASE) has reportedly obtained orders for fan-out wafer-level packaging (FOWLP) from Qualcomm, MediaTek and HiSilicon with volume production set...

PTI buys wafer-level packaging equipment

Stockwatch - Sep 28, 14:08

Packaging and testing company Powertech Technology has purchased wafer-level packaging equipment from Ultratech SE Asia for NT$544 million (US$17 million), according to a company...

Applied Materials, IME to advance R&D in fan-out wafer-level packaging

Sep 20, 00:46

Applied Materials and the Institute of Microelectronics (IME), a research institute under Singapore's Agency for Science, Technology and Research, have announced a five-year extension...

STATS ChipPAC fan-out wafer-level packaging shipments exceed 1 billion units

May 11, 14:45

STATS ChipPAC has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded wafer-level ball grid array (eWLB), according to the company...

Cypress subsidiary Deca to receive US$60 million investment from ASE

Apr 28, 21:22

Advanced Semiconductor Engineering (ASE) and Deca Technologies, a subsidiary of Cypress Semiconductor, have announced the signing of an agreement whereby ASE will invest US$60 million...

Cadence launches complete IC packaging design and analysis solutions for fan-out WLCSP

Mar 16, 11:03

Cadence Design Systems has announced the availability of foundry-proven IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and...

TSMC expects to launch 5nm node 2 years after 7nm

Jan 18, 10:30

TSMC will be ready to roll out its 5nm process technology two years after the launch of its 7nm node, according to the pure-play foundry.

TSMC chairman Morris Chang is confident that the company will lead the 10nm foundry market segment

Advanced semiconductor packaging drives materials consumption through 2019, says SEMI

Dec 15, 15:54

The US$18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC...

TSMC to provide backend InFO packaging technology for Apple chips, says report

Newswatch - Dec 11, 10:48

TSMC is scheduled to move its integrated fan-out (InFO) wafer-level packaging technology to volume production in the second quarter of 2016. Apple will be among the first wave of...

Cadence offers design tools for TSMC InFO packaging

Sep 23, 15:58

Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated...

Xintec profits soar in 1Q15

Stockwatch - May 21, 21:23

Taiwan's Xintec, an affiliate of Taiwan Semiconductor Manufacturing Company (TSMC) specializing in packaging services for CMOS image sensors as well as MEMS and fingerprint sensors,...

TSMC InFO-WLP technology to generate significant revenues starting 2016

May 5, 22:25

Taiwan Semiconductor Manufacturing Company's (TSMC) backend integrated fan-out (InFO) wafer-level packaging (WLP) technology will start contributing significantly to the IC foundry's...

Altera, TSMC develop UBM-free WLCSP packaging

Apr 7, 21:30

Altera and TSMC have produced an UBM-free (under-bump metallization-free) WLCSP (wafer-level chip scale package) technology for Altera's MAX 10 FPGA products, according to the comp...

Xintec 12-inch wafer-level CSP ready for volume production in 2H15, says chairman

Mar 17, 20:01

Image sensor packaging house Xintec will have its 12-inch wafer-level chip-scale package (WL-CSP) line ready for volume production in the second half of 2015, according to company...

Xintec chairman Robert Kuan

TSMC to offer InFO-WLP technology for 16nm chips, eyeing Apple orders

Feb 4, 13:45

Taiwan Semiconductor Manufacturing Company (TSMC) will have its backend integrated fan-out (InFO) wafer-level packaging (WLP) technology ready for 16nm chips, eyeing orders for Apple's...

UTAC said to set up 12-inch wafer-level packaging line in Taiwan

Dec 23, 15:13

United Test and Assembly Center (UTAC), a Singapore-based assembly and test company, will continue its investment in Taiwan in 2015 by setting up a 12-inch wafer-level packaging line,...

High-end packaging next battlefield for IC assembly and test services providers, says Amkor executive

Jul 9, 15:53

Robust growth in smartphone usage is encouraging semiconductor assembly and test services providers to head towards related packaging technologies. Amkor Technology is already among...

Kevin Yu, Amkor sales director for Greater China

STATS ChipPAC to pump another US$500 million into expansion in Singapore

May 29, 11:19

STATS ChipPAC has unveiled plans to invest another US$500 million to expand its operations in Singapore, where the IC backend house is headquartered.

Scientech deepens development of 3D IC, wafer-level packaging equipment

Jan 31, 16:04

Taiwan-based semiconductor equipment distributor Scientech has deepened its development of 3D IC packaging and wafer-level packaging equipment, expecting some of its equipment to...

ChipMOS expects sales growth in 2012

Mar 19, 16:15

Packaging and testing firm ChipMOS Technologies has forecast consolidated revenues for 2012 will increase 10%. The company revealed that net revenues on a US GAAP basis for 2011 grew...

Aptos expanding 12-inch wafer level packaging business

Mar 14, 14:30

Aptos Technology, which specializes in backend services for the production of NAND flash chips and devices such as microSD cards, announced March 13 that two of its subsidiaries will...

STATS ChipPAC intros new 3D eWLB PoP solutions

Mar 7, 11:35

STATS ChipPAC, a semiconductor test and advanced packaging service provider, has announced its next-generation three dimensional (3D) embedded wafer-level ball grid array (eWLB) package-on-package...

STATS ChipPAC breaks ground for new factory

Jan 6, 01:20

STATS ChipPAC on January 5 hold a groundbreaking ceremony for its new factory in Singapore, according to the chip test and packaging service provider. The new 197,000-square foot...

Focus on small, cost-effective packages: Q&A with STATS ChipPAC CEO Tan Lay Koon

Nov 21, 13:48

Despite uncertainties in the semiconductor industry outlook, packaging and testing firm STATS ChipPAC will continue investing in advanced IC packages for space-critical designs that...

STATS ChipPAC CEO Tan Lay Koon

STATS ChipPAC to open new wafer-level packaging plant in Taiwan, says paper

Newswatch - Nov 14, 16:40

STATS ChipPAC is scheduled to hold an inauguration ceremony for a 12-inch wafer bumping and wafer-level packaging plant in Hsinchu County, northern Taiwan, Thursday (November 17),...

PTI developing advanced packaging technologies

Jul 1, 01:10

Packaging and testing firm Powertech Technology (PTI) expects the development of new technologies including wafer-level packaging, 3D IC packaging and copper pillar bumping to bear...

ASE aims at global market share of 25-30% in 2014

Jun 29, 01:00

IC packaging/testing service provider Advanced Semiconductor Engineering (ASE) aims to hike its global market share from 17-18% in 2010 to 25-30% in 2014, COO Tien Wu said at the...

STATS ChipPAC expands WLP offering with 12-inch manufacturing in Taiwan

Jan 18, 12:00

STATS ChipPAC has announced the expansion of its wafer-level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan. The 300mm WLP operation is located in Hsinchu...

ASE to budget US$700 million in capex for 2011, says paper

Newswatch - Oct 4, 17:00

IC packaging and testing house Advanced Semiconductor Engineering (ASE) plans to budget US$700 million in capex for 2011, flat on year, an unnamed company executive has been cited...

STATS ChipPAC opens new plant for 300mm eWLB wafer manufacturing

Sep 15, 15:33

STATS ChipPAC on September 15 celebrated the opening of a new manufacturing facility to process 300mm wafers using embedded wafer-level BGA (eWLB) technology. The Singapore-based...

40 items [1/2]
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China AMOLED panel capacity expansion forecast, 2016-2020

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