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News tagged Cadence
  • Last update: Tuesday 13 October 2015 [28 news items]

Cadence announces memory model for LPDDR5

Oct 13, 14:39

Cadence Design Systems has announced the Cadence Memory Model for the LPDDR5 standard. This new verification IP (VIP) product enables engineers to verify that system-on-chip (SoC)...

Imec and Cadence complete tapeout of first 5nm test chip

Oct 8, 10:08

Nano-electronics research center imec and Cadence Design Systems have announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as...

Cadence offers design tools for TSMC InFO packaging

Sep 23, 15:58

Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated...

Cadence announces IP portfolio for TSMC 10nm FinFET process

Sep 17, 15:46

Cadence Design Systems has announced an intellectual property (IP) portfolio for TSMC's 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio...

Realtek accelerates SoC verification with Cadence Palladium XP platform

Aug 11, 20:07

Cadence Design Systems has announced that Realtek Semiconductor utilized the Cadence Palladium XP platform to accelerate the development and verification of a recent system-on-chip...

Cadence, TSMC collaborate on IoT IP subsystem

Jun 9, 11:20

Cadence Design Systems has announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) IP subsystem demonstration platform for TSMC's ultra-low...

Cadence implementation and signoff tools certified on Intel 14nm Process

Jun 5, 15:09

Cadence Design Systems has announced that its implementation and signoff tools have achieved certification on the Intel 14nm process for customers of Intel Custom Foundry. Intel Custom...

Globalfoundries announces design infrastructure for 14nm FinFET process

Jun 3, 12:15

In collaboration with design ecosystem partners, Globalfoundries has announced the availability of digital design flows for customers designing on its latest manufacturing technology...

Cadence digital and custom/analog tools achieve TSMC certification for 10nm FinFET early design starts

Apr 9, 22:07

Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most-current version of 10nm FinFET Design Rule Manual...

Cadence and Intel collaborate to release 14nm library characterization reference flow

Mar 18, 15:15

Cadence Design Systems and Intel have delivered a 14nm library characterization reference flow for customers of Intel Custom Foundry, continuing their collaboration on enabling digital...

Global Unichip utilizes Cadence analog IP to implement WiGig-enabled SoC on 28nm process

Mar 5, 22:17

Cadence Design Systems has announced that Global Unichip achieved first-silicon success integrating tri-band analog front-end (AFE) intellectual property (IP) with WiGig (IEEE 802.11ad),...

UMC and Cadence collaborate to deliver 28nm design reference flow for ARM Cortex-A7 MPCore-based SoC

Jan 21, 13:49

Cadence Design Systems has announced that United Microelectronics (UMC) used its implementation and signoff tools to produce a silicon-ready 28nm ARM Cortex-A7 MPCore-based System-on-Chip...

Globalfoundries and Cadence deliver first SoC enablement solution featuring ARM Cortex-A17 processor in 28nm-SLP process

Dec 18, 21:58

Cadence Design Systems and Globalfoundries have jointly announced the delivery of quad-core silicon built around the ARM Cortex-A17 processor implemented using Globlfoundries' 28nm...

HiSilicon expands adoption of Cadence tools and IP for advanced-node FinFET designs

Dec 2, 14:38

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for...

VIA licenses Cadence Tensilica HiFi audio/voice DSP

Oct 23, 11:08

Cadence Design Systems has announced that VIA Technologies has selected the Cadence Tensilica HiFi audio/voice digital signal processor for a system-on-chip design for set-top boxes,...

ARM buys mobile display IC cores from Cadence

Sep 4, 15:02

Processor IP licensor ARM and Cadence Design Systems, an EDA tool company, have signed an agreement for the sale and transfer of Cadence PANTA display controller cores to ARM, according...

Blue-collar processing: Q&A with Tensilica founder Chris Rowen

Jun 28, 16:12

Based in Santa Clara, Tensilica has been around the semiconductor industry for around 15 years, providing customers with what it calls configurable dataplane processors (DPUs). The...

Chris Rowen, chief technology officer and founder of Tensilica<br>

20nm process to take off in 2013, says Cadence executive

Apr 19, 15:15

The semiconductor industry will accelerate towards the adoption of 28nm process in 2012, and begin its transition to the next technology node in 2013, according to Chi-Ping Hsu, a...

Globalfoundries tapes out 20nm test chip

Aug 30, 16:40

Globalfoundries has announced that it successfully taped out a 20nm test chip using flows from EDA partners Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys...

Samsung Foundry tapes out 20nm

Jul 13, 01:00

Samsung Electronics has announced that its foundry business, Samsung Foundry, successfully taped-out a test chip based on its 20nm process with high-k metal gate (HKMG) technology...

TSMC delivers interoperable EDA formats for advanced process technologies

Apr 8, 10:40

Taiwan Semiconductor Manufacturing Company (TSMC) has made available several unified and interoperable electronic design automation (EDA) technology files for its 65nm, 40nm and 28nm...

EDA providers reshuffle management in Asia Pacific

Newswatch - Jul 13, 14:48

Another electronic design automation (EDA) provider is reshuffling its Asia-Pacific operations, following recent regional head changes at Cadence Design Systems and Synopsys, according...

Global Unichip to have former Cadence Asia Pacific president head China operations

Jun 30, 12:07

Taiwan-based IC design service provider Global Unichip has decided to appoint Lung Chu, the former Asia Pacific president for EDS company Cadence Design Systems, as its China president...


Global Unichip beefing up presence in China, Japan and South Korea

Jun 4, 12:18

Taiwan IC design service provider Global Unichip will strengthen its deployments in China, South Korea, Japan, Europe and Israel in 2009, according to company CEO KC Shih. Market...

Lung Chu

SiS joins power forward initiative to assist in delivering power-efficient computing platforms

Mar 13, 13:58

Silicon Integrated System (SiS) has announced its joining of the Power Forward Initiative (PFI) and plans to offer common power format (CPF) design solutions for its chipset, motherboard,...

China IC design industry should strengthen R&D amid economic downturn, says Cadence executive

Jan 12, 15:59

China's IC design houses should strengthen their R&D in order to gain competitiveness within their home market against foreign rivals, when developed markets such as Europe and...

Cadence Asia president Lung Chu

MEMS to bring in NT$50 billion, says president of Cadence Asia Lung Chu

Dec 24, 15:59

MEMS is expected to bring in sales worth NT$50 billion (US$1.5 billion) as long as MEMS components can be produced on a large scale, according to Lung Chu, president of Asia Pacific...

Commentary: Low price strategy limits growth potential of players in China's IC design industry, says president of Cadence Asia

Jul 16, 11:25

Facing emerging competitors from China, IC design companies in Taiwan constantly enhance their products and operation to keep the advantageous position in the IC design field, according...

Lung Chu, the president of Asia Pacific Field Operations, Corporate Vice President in Cadence.
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