New industrial control technologies and applications for flash memory in 2013
Sponsored content [Friday 15 March 2013]
The quality and durability of successive generations of flash memories have tended to drop. Industrial customers are often only willing to use costly SLC memory, which limits SSD capacities for industrial control applications. The flash SSD/DOM industry has incorporated iSLC memory technology which is 10 times more durable than MLC, as well as key technologies that can maintain and monitor program/erase (P/E) wear leveling. This allows MLC to be integrated into lightweight industrial control applications, while iSLC memory will become the new darling of industrial control applications.
The challenges of MLC in embedded industrial applications
As production processes have advanced, the line width and spacing of NAND flash have become increasingly smaller, which has reduced the number of P/E cycles. Taking SLC memory as an example: the 100,000 P/E cycles of 3xnm process era chips required only four ECC (error correction code) bits; while the P/E cycles for SLC in the 2xnm process era have reduced to 60,000 and 24 ECC bits are required.
The early 5xnm production process MLC flash required eight ECC bits with 10,000 P/E cycles, and during the 3xnm MLC era, P/E cycles were reduced to 5,000 while ECC significantly increased to 15 bits. During the 2xnm MLC era, P/E cycle have fallen to 3,000 and ECC expanded to 24 bits, and 2ynm node MLC requires 40 ECC bits.
Transmission rates of peripheral storage devices have also continuously improved. In 2010, ONFI 2.0 was advanced to 133MB/s and transmission rates of eMMC v4.41 were 104MB/s. In 2011, the ONFI v2.2/Toggle 1.0 specification increased flash transfer rates up to 200MB/s, the eMMC v4.5 was raised up to 200MB/s, while the transfer rate of UFS 1.0 was 2.9Gbps, and the SATAII specification was 3Gbps (300MB/s). In 2012, the ONFI v3.0/Toggle v1.5 specification raised flash transfer rates up to 400MB/s, UFS v2.0 transfer rates doubled to 5.8Gbps, and the SATAIII specification jumped to 6Gbps (600MB/s). By 2015, the transmission rate of the ONFI v4.x/Toggle v2.xx specification is expected to increase to 800MB/s and 1.6GB/s.
Facing the various challenges from the declining durability/quality of flash
CC Wu, Director of Embedded Flash Business Division at InnoDisk, listed the challenges of the MLC memory as follows: The number of error bits continues to increase; 40 ECC bits are needed at the 2ynm node and the number will continue to increase at temperatures around the negative 40 to 85 degree C range. Meanwhile, sudden power interruptions during power cycling often cause data to become lost, the lifespan of data decreases as P/E cycles increase, and the 16K paging design of MLC takes a significant amount of processing time for garbage collection.
If customers want to integrate MLC into lightweight industrial control applications, good P/E wear leveling and internal monitoring tools are required, in addition to other complementary technologies.
As the number of P/E cycles increases, error units also increase. Taking 3xnm MLC as an example: according to internal long-term test results performed by InnoDisk, an average of one error will occur within 1,000 P/E cycles. Beyond 20,000 P/E cycles, the number of errors increases five-fold. For 2xnm MLC, the average number of errors for less than 1,000 P/E cycles is already five, and the errors increase to 25 for 8,000 P/E cycles. For 2ynm process MLC, the number of errors is three for 1,000 P/E cycles, 34 for 8,000 P/E cycles, and 41 for 10,000 P/E cycles.
InnoDisk indicated that flash Correct-and-Refresh (FCR) technology can read and monitor MLC blocks where the occurrence rate of errors has increased, fix the error bits, and store them in better conditioned blocks, and then restart the P/E cycle to improve the service life of the flash. InnoDisk has also developed smarter garbage collection algorithms for 16KB paging MLC flash to reduce the SSD data maintenance delay phenomena.
Wu believes that during access to MLC memory, dynamic wear-leveling technology can be used in combination with static wear-leveling technology which is especially critical for MLC with just 3,000 P/E cycles. InnoDisk has provided an iSMART utility program that can illustrate the number of times an SSD block has been written to, and illustrate the overall wear-leveling effects. It can also monitor temperatures, estimate service life, and provide performance monitoring and pre-warning functions.
If a sudden power outage occurs when MLC is writing data and the firmware is performing data writing or garbage collection, it is likely to cause damage to the memory page where the data is being written, and the adjacent memory pages, and may even cause the entire SSD's data to become lost. Therefore, a good SSD controller must have failure/low-voltage detection circuits that can quickly finish writing data to memory pages and save any necessary system-state data for restoration, in order to enable a reboot when a drop in input current voltage is detected.
Using iSLC to provide low-cost and high-quality industrial control applications
Industrial control applications under general commercial temperatures (0 to 70 degrees C) require constant read/write capabilities and a five-year quality guarantee. Customers mostly choose SLC for heavyweight intensive read/write applications. However, SLC costs almost five times more than MLC. Therefore, InnoDisk has proposed the iSLC memory solution.
iSLC has the advantages of both SLC and MLC. It is produced using existing low cost MLC memory process technology, and has SLC-like read/write capabilities (each charge stores only 1-bit). Therefore, endurance is improved to 30,000 P/E cycles, falling between the 60,000 P/E cycles for SLC and 3,000 P/E cycles for MLC. Although iSLC involves higher costs than MLC, it is half the cost of SLC and can be applied to IPC/kiosk/POS systems, embedded systems, server boards, thin terminals, etc.
Wu illustrated a long-term durability test chart for MLC and iSLC produced under the same 2xnm process. The results showed that after 20,000 continuous data writes, MLC generated over 30 errors while iSLC generated only six. Even after 100,000 continuous P/E cycles, iSLC generated less than 10 errors and its durability and quality are comparable to those of the SLC memory created under standard SLC processes. The results for 32GB SSD tests showed that when 32GB of data is written 10 times each day, MLC can only be maintained for 0.8 years, 3xnm SLC can reach 27.4 years, 2xnm SLC can reach 16.4 years, and 2xnm iSLC can reach 7.6 years.
InnoDisk has designed a series of products using iSLC flash memory technology for the SATAII interface. Its 2.5-inch SSD 2IE model adopts an 8-channel design, offers between 32GB and 256GB capacities, and has a sustained write speed of between 200MB/s to 230MB/s; the SATADOM-QVL 2IE and SATADOM-QV 2IE models adopt 4-channel designs, come in 8GB to 64GB capacities, and have sustained write speeds of between 120MB/s to 130MB/s; and the CFAST 2IE adopts a 4-channel design, capacities between 8GB and 64GB, and has a sustained write speed of between 120MB/s to 130MB/s. In addition, the company offers 2IE mSATA, Slim 2IE, and SATADOM QH 2IE modules that adopt a 4-channel SATAII design, come in 8GB to 64GB capacities, and offer sustained write speeds of between 120MB/s and 130MB/s.
SATAIII solutions for embedded applications
Wu then introduced SATAIII product solutions for embedded industrial control applications. The InnoDisk ID167 control chip developed by InnoDisk adopts a 4-channel 8CE design, and has an ECC data correction capability of 40bit/1KB. It uses a 64MB 16-bit DDR III memory read/write buffer and consumes between 5mW and 33mW of power under SATAIII slumber and DEVSEL modes. SSD and mSATA modules designed with the ID167 will begin sampling during the first quarter of 2013.
InnoDisk's ID167 adopts 24/25nm process Sync MLC flash memory chips. Under IO Meter performance test, the 64GB (4CH) version delivers sequential read/write performance of between 270MB/s and 480MB/s and sustained read/write IOPS are 1K and 80K. The 128GB (4CH) version, offers sequential read/write performance between 350MB/s and 520MB/s and sustained read/write IOPS are 2K and 80K. For the 256GB (4CH) version, sequential read/write performance can reach between 400MB/s and 550MB/s and sustained read/write IOPS are 3K and 80K.
Compared to 128GB SLC SSDs used in mainstream industrial control applications, CystalDiskMark v3.0 test results indicate that the sequential read/write speeds of the 256GB MLC SATAIII SSD are 519MB/s and 344MB/s, respectively; and the sequential read/write speeds for the Pure SATAII 128GB SLC SSD are 253MB/s and 190MB/s, respectively. At similar costs, the 256GB MLC SATAIII SSD has twice the capacity and faster performance compared to those of the 128GB SLC SATAII SSD.
InnoDisk also provides single-chip modules. The 32GB (4CHx1CE) comprises the InnoDisk ID167 controller chip with a flash silicon wafer chip on board (COB) package. The device has sequential read/write speeds of 480MB/s and 140MB/s, respectively. When CystalDiskMark v3.0 performance tests are conducted to compare performance against the 32GB SATADOM SATAII SLC, the sequential read/write speeds of the SATAIII device are 482MB/s and 271MB/s, respectively; and the SATAII sequential read/write speeds are 252MB/s and 235MB/s, respectively.
CC Wu, director of embedded flash business division at InnoDisk