SSD controller SoC operated in a multi-threaded CPU environment can achieve cost optimization goals, says MIPS
Sponsored content [Wednesday 14 March 2012]
The SSD controller market is rapidly expanding, creating huge opportunities for the semiconductor industry. However, the design of complex chips and ever-increasing performance/functional requirements has also posed a challenge in terms of costs and efficiency to the industry players. MIPS has brought up the idea of having the chips operated in a multi-threading CPU environment to address these design challenges. And in the future, the company expects to remain the leading provider of processor architectures and cores for digital home and networking applications, and will actively pursue development in the emerging mobile market.
The SSD market has witnessed an amazing rate of growth thanks to a surge in popularity of lightweight and thin multimedia mobile devices, extensive applications of cloud computing and social app platforms, significantly increasing demand for audio and video data storage requirements. According to data compiled by Forward Insights, SSD shipments will climb to 120 million units in 2014 from only 20 million in 2011. Judging from the recent spree of acquisitions and mergers in the IT industry, a number of enterprises are showing their optimism about how owning SSD technologies will help create competitive advantage. SoC suppliers should seize the opportunity to win a seat in this changing market, providing various high value-added solutions, said Del Rodillas, director of vertical marketing at MIPS.
SSD designed to strike a balance between size, energy consumption and performance
However, producing the best set of SSD controllers to meet the trends is hard. Developers confront a number of design challenges including raising the bar for I/O speed (the latest version of SATA Express delivers data transfer rate of 8-16Gbps), and enabling management support for more information, more complex features (such as hybrid storage devices for ultrabooks) as well as error data correction capability, encryption/ decryption and safety procedures, and data stream priority and control (such as, specifying a higher priority for voice traffic than for data). Those design issues will greatly increase the difficulty in designing SSD controllers. Ways to extend the performance of SSD controllers under limited cost and energy supply conditions will be the problem developers have to overcome in the first place, said Rodillas.
Up until now, the CPU has been the most important computing engines for SSD controllers, Rodillas continued. However, having SSD controllers run with a conventional single-core CPU structure has encountered bottlenecks, such as, advancing the performance of real-time processing makes it unlikely to make further progress, Rodillas said. He explained that SSDs have too many features needed to operate in parallel (such as NAND layer adaption, power management, wear leveling, NCQ, bad block management, garbage collection, traffic management & routing, etc.), which a single-core CPU architecture is unable to cope with. Though some companies alternatively use multi-core CPU designs, this will only result in increases in silicon area and power.
Facing intense competition and a more challenging market environment, device manufacturers - particularly those specializing in mobile communications products - are aware that the ability to make products at the lowest possible costs while meeting specific dimensions and performance, and energy saving requirements is the key to winning customers.
Therefore, in order to assist the industry to solve the problems, MIPS has introduced its multi-threaded processor core enabling one CPU to process multiple threads at a time. The capability does maximize the utilization of computing resources and improve system performance, Rodillas indicated. The CPU acts as an already-high efficient single execution pipeline, which does not require additional counterparts, and simultaneous multi-threading helps it further improve performance efficiency, Rodillas said.
MIPS multi-threaded CPU core can assist the industry to address these design challenges
MIPS' multi-threaded core solution for embedded applications incorporates several hardware virtual processing elements (VPEs) containing thread contexts (TCs) - used to further increase the number of hardware threads. Therefore, through multi-threading, developers no longer need to add full hardware required for implementing another VPE.
In addition, MIPS' multi-threaded core offers an efficient inter-thread communication mechanism for implementing high-performance data flow. Another capability is the zero-overhead interrupt support, which can be implemented through letting a thread "park" until an external event signals it to resume execution. These management tools allow users to execute instructions from multiple threads and ease management of real-time behavior. These unique features would be helpful for enhancing the quality of services (QoS) of end-market products.
For example, a single-threaded CPU architecture consists of functional units such as MDU, ALU, LD/ST, ICU and MCU, as well as a translation lookaside buffer (TLB) responsible for virtual to physical address translations. Software must get the access to user and PRA registers to understand the CPU status. With the concept of virtual processors in the MIPS architecture, each virtual processor will obtain duplicate user and PRA registers, a TLB and program counter to share the resources of execution units.
For software, the solution is tantamount to the existence of more than one complete processor, and can speed up the processing efficiency of the pipeline without increasing the area and power. Multi-threading can also be used in Linux-powered devices to develop multi-core programming solutions.
MIPS has used the BrowsingBench benchmark from EEMBC - which provides an industry-accepted method of evaluating Web browser performance on smartphones, netbooks, portable gaming devices, navigation devices and IP set-top boxes - to evaluate the performance benefits of its multi-threading core solutions, according to Rodillas. Results show that Android-based web browsing performance is greatly enhanced by the technology. Within single-core CPU architecture, the MIPS multi-threading technology boosts the performance 43% through two VPEs. The performance will be 2X higher when the configuration is dual-core with two VPEs per core. A dual-core, 4-VPE system delivers 2.5X the performance of a single core. Therefore, a SSD operated in the MIP dual-core, multi-threaded CPU environment is able to see its efficiency improve 44%, save 57% more in power consumption and a dimension reduction of 43% when compared to rivals' fellow products. Systems operated in a single-core, multi-threading environment will be superior in terms of performance efficiency (up 55%), energy use (down 57%) and size (49% smaller).
MIPS multi-threaded core adopted by many companies for their products
According to market watchers, 33% of the products shipping with mid-range to high-end MIPS cores are multi-threaded ones. For instance, Ralink's ADSL Internet access device is based on MIPS' multi-threaded architecture to enable more applications and ensure high QoS for its products. "With this architecture, Ralink is able to efficiently provide deterministic VoIP response and support for multiple applications in a single device," Ralink said.
Mobileye also uses the MIPS multi-threaded core in the chips inside the company's driver assistant systems - the EyeQ2 vision-based SoC series - for luxury cars such as the Volvo S60 and BMW. "MIPS' multi-threaded 34K cores helped us achieve a 6x performance increase in the EyeQ2 vision chip over the prior generation," Mobileye said. In addiiton, the PWC-Sierra PM8013 maxSAS RAID-on-Chip controller comes with three multi-threaded MIPS cores. "The multi-threading MIPS 34K cores deliver performance higher than any other RAID solution," according to PWC-Sierra.
MIPS is a leading global provider of industry-standard processor architectures and cores (Kernel), providing optimized structures that are cost efficient, meet their applications' scalability needs, and allow system developers to produce their next-generation solutions at lower risk. MIPS' architectures has become the standard in the embedded industry.
According to the information provided by MIPS and industry analysts, MIPS provides the number one processor architecture for markets including digital TVs, cable/satellite/IPTV set-top boxes, Blu-ray Disc players, broadband consumer premises equipment (CPE) and Wi-Fi access points/routers. MIPS-based designs are integrated into tens of millions of products around the world.
Rodillas stated that MIPS' growth strategy is targeting three key markets - the digital home, wired/wireless network and mobile communication. MIPS is committed to developing multi-core, multi-threaded and 64-bit technologies for high-end broadband CPE and WAN LAN applications. The company has also been investing heavily in the development of its ecosystem of partners dedicated to developing connected devices in order to maintain its existing lead in the digital home and networking market segment, Rodillas continued. Meanwhile, MIPS is currently working with a number of Android and 4G device companies, and has been actively developing its presence in the emerging mobile communications field looking to end the dominance of ARM architectures. Cisco, Hewlett-Packard, Huaya Microelectronics, Linksys, Microchip Technology, Motorola, Pioneer and Sony are among MIPS' important partners.
Del Rodillas, director of vertical marketing at MIPS
Rodillas demos the latest SSD controller SoCs operated in a multi-threading CPU architecture at the MIPS booth