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The flash memory interface - Standardization, low-pin count and high performance
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Thursday 1 August 2013

Supported by a number of different interfaces and standards, flash memory can be custom-designed for a variety of applications. Earlier designs mostly adopted the parallel bus architecture. However, demand for lighter and thinner mobile devices has been prompting the industry to simplify flash interfaces. Serial designs have enabled smaller-size flash memory with lower pin counts, and there are even mixed NOR-NAND designs. These have helped simplify the PCB layout, reducing costs for applications targeting the embedded market. The NAND flash manufacturing process may be approaching its limits, but Macronix has demonstrated its R&D strengths with new-generation memory technologies, such as PCM and ReRAM.

Macronix and the evolution of flash memory technology

Memory for today's mobile devices and embedded systems are primarily flash-based, and there are two major types: NOR and NAND. NOR is primarily used to store firmware codes that are changed less often, and NAND is primarily used to store large volumes of data frequently accessed by users. Flash memory makers have been taking part in the making of new transmission standards that can be incorporated into next-generation SoC designs. This will accelerate the development of embedded products.

Gabriel Chou, Project Manager at Macronix International, was invited to this forum to introduce his company's products. Chou indicated that Macronix is a leader in ROM and flash memory: It is number one in worldwide ROM shipments, number two in worldwide serial flash shipments, and number three in worldwide NOR flash shipments.

The popularity of mobile devices, with many users owning more than one, is driving flash memory growth to over 17% annually, and storage capacities have been growing exponentially, Chou noted. He illustrated the trend with the development of non-volatile memory (NVM), a sector where Macronix is an expert. From the early EEPROM with capacities measured in KB to the later NOR with capacities measured in MB, these devices were primarily meant for storing codes. But SLC/MLC/TLC NAND/ROM (and the new-generation PCM and RRAM) devices are primarily meant for data storage and their capacities have expanded to the GB level. Future 3D NAND will have capacities approaching the TB level.

Flash memory interfaces: Simplicity, high efficiency, and low power consumption

Chou went on to explain the evolution of the flash interfaces. Parallel NOR and NAND used to be primary type. But as the parallel design required high pin counts, the serial (or SPI bus) type later became the more favored design in order to achieve lower pin counts. However, the industry has now adopted the designs of dual and four I/O buses, and it is also looking at eight I/O buses for future applications. For storage interfaces, there are SATA and eMMC, plus the future UFS specification.

Chou indicated that Macronix has seen diminishing shipments for parallel (AD-MUX or page mode) NOR and parallel NAND, and gradually rising shipments for SPI-NOR and SPI-NAND. This clearly shows that the industry is shifting to simplified designs with reduced pin counts, as well as more I/O buses and higher efficiency. The standard eMMC/UFS is expected to be the mainstream soon for 3C products with large memory capacities. As for LPDDR, Chou stated that it remains to be seen whether this interface will become popular in the future.

What is worth noting is that the evolution of eMMC is actually very similar to that of SPI. That is, after the number of I/O buses has increased to eight, SPIx8 can reach a transmission speed of 1.6Gbps; and after the DDR mechanism has been added to the eMMC v5.0, it can reach HS400x8 (3.2Gbps).

The mixed-type flash memory interface design

Each type of memory technology (EEPROM, PCM, ROM, NOR, and NAND) has its dedicated transmission interface and controller. Manufacturers have standardized them to simplify designs and accelerate product development.

However, as the NAND flash production process moves towards 2Xnm or even 1Xnm nodes, it must be supported by better controllers to provide greater stability and higher-bit error checking and correction (ECC). This enables reliable data storage.

Because there are different types of memory, the trend is to provide modules with interfaces standardized through the controller.

HybridFlash launched by Macronix in 2012 is based on such a concept. It integrates XtraRom, serial flash, and the controller into a single multi-chip package (MCP), and uses the eMMC or SPI interface for transmission. MCP supports embedded systems' OS, various codes and transmission interfaces. It offers flexibility and reliability, as well as competitive pricing. Currently, it is available in capacities ranging from 2Gb to 8Gb.

The direction of future memory development

Macronix has spared no effort in R&D and innovation. In 2012, 19% of its investments went to R&D. Macronix has obtained more than 5,000 patents, making it the world's number 18 IT firm in terms of patent portfolios. In various memory-related technology forums, Macronix has also outnumbered its peers in terms of papers published on floating gate, charge trapping, and NVM technologies, as well as new-generation memories such as phase change memory (PCM, co-developed with IBM) and resistive random-access memory (ReRAM). This demonstrates Macronix' expertise in the NVM field.

Macronix has also developed the world's smallest vertical gate (VG) 3D NAND memory. The present 37.5nm process can stack up to eight layers of memory chips. Within the next three years, Macronix will move towards 36nm and 2Xnm in order to meet the demand for smaller mobile devices with larger capacities.

Gabriel Chou, Project Manager at Macronix International

Gabriel Chou, Project Manager at Macronix International

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