Calypto recently launched its Catapult 8 platform, a third-generation, high-level synthesis (HLS) technology, which the company claims is the first in the industry.
According to Calypto, the Catapult 8 platform gives designers control over which regions are optimized, and the ability to work "top down" or "bottom up", which is required to be able to integrate RTL IP. Previous generation HLS tools implemented effective top down optimization techniques, but lacked capabilities to easily fit into complex design flows and standard verification methodologies.
The claim of Calypto is that the new Catapult 8 database and smart caching techniques provide at least a 10X capacity improvement, making the synthesis of large subsystems possible.
The synthesized RTL is now optimized for power and verification requirements, in addition to meeting area and performance constraints. Verification-optimized RTL is code that is ready to be deployed into industry and corporate standard verification flows, including flows based on UVM. In addition, the new architecture was expressly built to natively support both SystemC and C++ as input languages.
Customers will be able to write either C++ or SystemC, depending on the design and verification needs of each project, and then use Catapult's configurable hierarchy technology, which makes it possible to synthesize much bigger designs. Catapult 8 can now efficiently synthesize our multi-million gate data processing hardware, said Emmanuel Liégeon, Head of ASIC/FPGA Design Group at Thales Alenia Space France.
Calypto will also continue supporting and enhancing its prior product until customers were ready to transition to the new architecture.