The PCI Special Interest Group (PCI-SIG) that owns and manages PCI specifications, has announced the availability of the PCI Express Base 2.0 specification. After a 60-day review of revision 0.9 of the specification in late 2006, members of the PCI-SIG finalized and released PCI Express (PCIe) 2.0, which doubles the interconnect bit rate from 2.5GT/s (gigatransfers per second) to 5GT/s to support high-bandwidth applications.
In addition to the faster signaling rate, PCI-SIG working groups also added several new protocol layer improvements to the PCIe Base 2.0 specification, such as dynamic link speed management (allows developers to control the speed at which the link is operating), link bandwidth notification (alerts platform software, including operating system and device drivers, of changes in link speed and width), capability structure expansion (increases control registers to better manage devices, slots and the interconnect), completion timeout control (allows developers to define a required disable mechanism for transaction timeouts), function-level reset (provides an optional mechanism to reset functions within a multi-function device) and power limit redefinition (enables slot power limit values to accommodate devices that consume higher power).
The PCIe Base 2.0 specification is available for download at the PCI-SIG website.





