Samsung Electronics may boost the production capacity of its CMOS image sensor by nearly 20% this year, analysts here said Sunday, as the South Korean tech giant tries to meet soaring demand.

Traditional semiconductor scaling is expected to reach an end by about 2024, according to a white paper from engineers working on a new version of the semiconductor roadmap. The good news is a wide variety of new kinds of devices, chip stacks and systems innovations promise to continue benefits in computing performance, power and cost.

Sony has announced the development of the industry's first 3-layer stacked CMOS image sensor with DRAM for smartphones.

The Crossbar ReRAM for embedded non-volatile memory applications is in production at partner foundry Semiconductor Manufacturing International (SMIC) using a 40nm CMOS process and is sampling to SMIC customers, according to Sylvain Dubois, Crossbar's VP of strategic marketing and business development.

Moore's Law may be coming to an end, but chipmakers and system designers continue to find ways to deliver better performance and integrate more features. In fact, as the industry approaches the fundamental limits of silicon CMOS technology, it seems to be getting more creative, not less. Over the next few years we are likely to see some revolutionary changes to system architecture.

SK Hynix made a plan to mass-produce 13 million-pixel CMOS Image Censor (CIS) from 300 wafer factory called M10, which is located in Icheon, in 2017.

Toshiba has announced the launch of "T4KB3", a 13-megapixel BSI CMOS image sensor with the optical format of 1/3.07 inch for smartphones and tablets. Sample shipments start today.

ARM has opened a new Design Center in Noida, North India. The center will focus on IP design in specialized areas such as planar and FinFET CMOS technologies and address the growing needs of ARM partners.

Avago Technologies has announced that its 28nm Serializer/Deserializer (SerDes) core has achieved 32Gbps performance while withstanding up to 40dB of channel loss.

The 55nm LPe 1V is especially suited for high-volume, battery-operated mobile consumer devices, as well as a broad range of green or energy-saving products. PDK and EDA tools are available now, along with MPW shuttle availability.

Sony has announced plans to invest in Sony Semiconductor's Nagasaki Technology Center from the first half of the fiscal year ending March 31, 2013 through the first half of the fiscal year ending March 31, 2014, to increase the production capacity for stacked CMOS image sensors.

Foundry Taiwan Semiconductor Manufacturing Co. has hit back at analysts who have said it has yield problems with its 28nm CMOS manufacturing processes.

Built using 40nm CMOS process technology, the new Broadcom BCM2079x family slashes power consumption by more than 90%, uses 40% fewer components and has a 40% smaller board area, making it the smallest and most power efficient NFC solution on the market.

OmniVision is promising an quarter-inch, 8-megapixel OV8850 CMOS sensor that the company says is 20% slimmer than any competing 8-megapixel module.

STMicroelectronics and CMP (Circuits Multi Projets) have announced that the CMOS 28nm process from STMicroelectronics is now available for prototyping to universities, research labs and companies through the silicon brokerage services provided by CMP.

"Recent data points have circulated in the past weeks suggesting OmniVision's BSI (backside illumination) yields have been adversely impacted out of TSMC, which could be backed-up on strong demand for general CMOS image sensors into smartphones and tablets," said analyst Doug Freedman of Gleacher & Co. in a new report.

Toshiba has developed a new flip-flop circuit using 40nm CMOS process that the company claims will reduce power consumption in mobile equipment. Measured data verifies that the power dissipation of the new flip-flop is up to 77% less than that of a conventional flip-flop and that it achieves a 24% reduction in total power consumption when applied to a wireless LAN chip.

Sony has announced plans to invest approximately 100 billion yen (US$1.2 billion) over the fiscal year ending March 31, 2012, to double its production capacity for CCD and CMOS image sensors. The investment plan includes the transfer of a plant from Toshiba.

Sematech has announced the completion of its 300mm 3D IC pilot line. Operating at the College of Nanoscale Science and Engineering's (CNSE) Albany NanoTech Complex, the pilot line includes all processes and test vehicles necessary to demonstrate the viability of the via-mid technology in conjunction with advanced CMOS.

The solution features Altera's low-cost Cyclone III or Cyclone IV FPGAs, and IP from Eyelytics and Apical supporting AltaSens' 1080p60 A3372E3-4T and Aptina's 720p60 MT9M033 HD wide dynamic range (WDR) CMOS image sensors.

Qualcomm has entered into a collaborative agreement with the global consortium of chipmakers. As the first fabless chip company to join Sematech, Qualcomm plans to participate in a high-level engagement to assess the feasibility of technologies that are designed to extend Moore's Law.

STMicroelectronics will be ready to tape out designs using a 20nm CMOS low power process technology in the fourth quarter of 2012, according to company CTO Jean-Marc Chery.

Professor Peter Denyer, a pioneer of CMOS imaging sensor technology for cameras, died of cancer on April 22.

If the current IC recovery will continue or fall back into a dreaded double dip, specialty foundry vendors also see a new competitive threat on the horizon: TSMC.

Hitachi researchers have developed a method to form cavities in the interconnect layers of CMOS ICs, allowing MEMS sensors to be created in the wiring layers.

The semiconductor memory industry is about to experience major technological changes as three-dimensional multi-gate structures push transistors and memory architectures forward, according to a one-day memory workshop held last month in Grenoble, France, by leading researchers from around the world.

Toshiba has announced a cost-effective 32nm CMOS platform technology, which allows to halve the cost per function from 45nm technology. The platform was achieved by application of advanced single exposure lithography and gate-first metal gate/high-K process technology. This technology enables a 0.124m(2) SRAM cell and a gate density of 3,650 gate/mm(2). The platform technology is based on a 32nm process technology developed jointly with NEC Electronics.