Huawei has reportedly completed work on electronic design automation (EDA) tools for laying out and making chips down to 14nm process nodes.

The UK has blocked the takeover of an electronic design company by a Hong Kong rival over national security concerns, in the latest sign of growing British anxiety about Chinese investment.

Synopsys has completed the acquisition of Gold Standard Simulations, a leading provider of TCAD and EDA simulation solutions for design technology co-optimization (DTCO) of advanced process nodes.

EDA and IP vendor Synopsys has introduced a new custom design tool that aims to help offset design challenges posed by the era of FinFETs with an intuitive concept dubbed visually assisted automation.

The 55nm LPe 1V is especially suited for high-volume, battery-operated mobile consumer devices, as well as a broad range of green or energy-saving products. PDK and EDA tools are available now, along with MPW shuttle availability.

Processors, memory, manufacturing processes, chip architecture, EDA, MEMS, RF, touch screens, servers and the Internet of Things are markets where startups can still make a difference.

The QFN package design kit enhances package modeling and simulation accuracy with Agilent's ADS electronic design automation (EDA) software for radio frequency (RF), microwave and high-speed digital applications for RF semiconductors.

Uniquify has become a TSMC Design Center Alliance (DCA) partner.

UMC has certified Synopsys' StarRC parasitic extraction solution for its latest 28nm process technologies, according to the EDA and IP vendor.

While global semiconductor revenue is projected to expand by 7.2% in 2011, Walden Rhines, chairman and CEO of EDA vendor Mentor Graphics, sounds a note of caution about maintaining this growth in 2012.

A conversation on August 20 with Joseph Sawicki, VP and GM of the Mentor Graphics Corp.'s Design to Silicon Division, provided a snapshot of the conundra facing foundries and EDA vendors as they approach sub-20nm process geometries. The landscape is filled with uncertainties, Sawicki warned, but there is no time left to wait for resolution.

Representatives from GlobalFoundries and TSMC said their companies are focused on tighter cooperation with EDA and IP vendors. The comments were part of a panel discussion at the Design, Automation and Test in Europe (DATE) conference, held last week in Dresden, Germany.

EDA vendors Mentor Graphics and Magma Design Automation have both reported quarterly revenues that exceeded Wall Street estimates and their own sales targets, but offered outlooks for the current quarter that fell short of analysts' expectations.

EDA company Mentor Graphics has entered into a multi-year software and services agreement with Globalfoundries which includes the provision of Calibre software for the design of 32nm and 28nm chips.

Cadence Design Systems and Globalfoundries have jointly announced a multi-year software and services agreement for advanced semiconductor design.

Software company Mentor Graphics has said it expects revenues and adjusted income in the third quarter to top Wall Street expectations.

EDA's industry "big three" held a panel session at DAC on the future of EDA and agreed that this is not "your father's recession."

Synopsys has announced that its DesignWare DDR3/2 PHY and digital controller IP is the first DDR3 IP that has been fully verified in test silicon at 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification. DesignWare DDR3/2 PHY and the digital controller IP are available now in advanced process technologies for foundries.

As if the current downturn weren't challenging enough, the semiconductor industry is also headed for increasing challenges from higher design costs and production at smaller geometries, according to Aart de Geus, chairman and CEO of Synopsys.

When George W Bush wanted a vice-president, he appointed Dick Cheney to head up a search team. When the team reported back, the selected candidate turned out to be…Dick Cheney. The Cadence board, having been a major contributor to Cadence’s problems through their selection of executive management and guidance given them, have also been off searching for a new CEO. And the selected candidate is…Lip-Bu Tan, member of the Cadence board.

Mentor Graphics has announced the qualification and immediate availability of its Olympus-SoC place-and-route system for chip designs targeting TSMC's 40nm process. These include the efficient 40nm (LP) process for handheld and wireless devices, and the 40nm General Purpose (G) for performance-oriented CPU, GPU, game consoles and networking devices.

Shares of microchip-design software maker Cadence Design Systems have lost almost 80 percent of their market value in the last 12 months as the company grapples with management changes, job cuts, a depleted cash flow and an aborted acquisition attempt. As expectations from investors seem to have bottomed and estimates have been cut significantly, the company is now positioned such that any positive incremental news can have a pronounced impact on the stock.